1. Technical Field
The present invention relates to a method for realizing a contact of a well, integrated in a semiconductor substrate, in particular for a base terminal of a bipolar transistor.
More specifically, the invention relates to a method for realizing a contact of a first well of a first type of dopant, integrated in a semiconductor substrate, next to a second well of a second type of dopant and forming with it a parasite diode.
The invention also relates to bipolar transistor and to a power actuator of the emitter-switched type comprising at least one high voltage bipolar transistor.
2. Description of the Related Art
As it is well known, a power actuator of the emitter-switched type is an electronic device able to supply a low voltage drop in conduction together with a high operative frequency.
In particular, as schematically shown in FIG. 1A, a power actuator of the emitter-switched type, globally indicated with 1, essentially comprises a high voltage bipolar transistor 2 and a low voltage DMOS transistor 3 connected in “cascode” configuration. In this way, the power actuator 1 has a collector terminal C, a base terminal B, a gate terminal G and a source terminal S. Such a power actuator is frequently indicated as ESBT® and represented by the equivalent circuit of FIG. 1B.
Thanks to the cascode configuration of the high voltage bipolar transistor 2 and of the low voltage DMOS transistor 3, the power actuator 1 has a low voltage drop in conduction and a high operative frequency, peculiarity that is more and more accentuated as the “voltage rating” of the actuator itself increases.
It is possible to integrate monolithically a power actuator 1 of the described type, as schematically shown in FIG. 2.
In particular, the monolithically integrated power actuator 1 comprises a substrate 5, realized by a first layer 5a heavily doped with a first type of dopant, in particular N, overlapped by a second layer 5b slightly doped with the first type of dopant N, commonly indicated as drift layer.
Above the substrate 5, a first buried layer 6 of a second type of dopant, in particular P, is realized, wherein a second buried layer 7 of the first type of dopant N, is then realized, in turn overhung by an epitaxial layer 8 of the first type of dopant N.
In the epitaxial layer 8, a low resistivity first 7a and second wells 7b of the first type of dopant N are realized suitable for contacting the second buried layer 7.
This second buried layer 7 and the wells 7a and 7b enclose a portion 9 of the epitaxial layer 8 wherein are formed first islands 10 of the second type of dopant P. Active areas of an elemental cell of the DMOS type are suitably realized, in particular in a second island 11 of the second type of dopant P, in turn realized in the first island 10 and overhung by at least one first contact structure 11a. 
A second contact structure 12a is realized above the portion 9 of the epitaxial layer 8, in correspondence with a tunnel region 12 of the elemental cell of the DMOS type.
Finally, the monolithically integrated power actuator 1 comprises a contact layer 12b, below the substrate 5, a first metallization layer 13 overhanging the well 6a and a second metallization layer 14 overhanging the first contact structure 11a and second contact structure 12a. 
In this way, the high voltage bipolar transistor 2 comprises a collector region realized by the drift layer 5b and contacted, by means of the first heavily doped layer 5a of the substrate 5 and the contact layer 12b, a base region realized by the first buried layer 6 and contacted by means of a well 6a of the second type of dopant P and the first metallization layer 13 and an emitter region realized by the second buried layer 7 and contacted by means of the well 7a. 
Hereafter the first buried layer 6 will be indicated as base region B and the second buried layer 7 as emitter region E, and the well 6a as base contact well and the well 7a as emitter contact well, this latter well being not contacted by a metal line. Further, the first metallization layer 13 will be indicated as base contact.
Moreover, the low voltage DMOS transistor 3 comprises a drain region coinciding with the emitter region E of the high voltage bipolar transistor 2 and realized by the portion 9 of the epitaxial layer 8, a source region S realized by the second island 11 and contacted by means of the first contact structure 11 a and the second metallization layer 14, a body region realized by the first island 10 and a control gate G realized by the second contact structure 12a. 
Hereafter then the first island will be indicated as body region, the second island 11 as source region and the first contact structure 11a as source contact structure, and the second contact structure 12a as gate contact structure. Further, the second metallization layer 14 will be indicated as source contact.
The monolithically integrated power actuator 1, as shown in FIG. 2, also has a symmetrical structure wherein the same regions, active areas and contact structures are arranged symmetrically with respect to the control gate G.
It is to be noted that this power actuator 1 however contains different parasitic components which worsen the performances.
The more insidious parasitic component is a parasitic diode, in particular a diode Dp connected between the base B and emitter E regions of the bipolar transistor 2, schematically shown in FIG. 3A, by means of its circuit equivalent, and in FIG. 3B, which shows an enlarged view of a portion of the monolithically integrated power actuator 1, as shown in FIG. 2.
It is to be noted that the figures showing schematic views of portions of the monolithically integrated power actuator 1 are not drawn to scale, but are instead drawn so as to highlight the important features of the description.
The efficiency level of this parasitic diode Dp easily causes such a worsening of the electric performances of the power actuator 1 that, during the design step of the corresponding integrated structure, an optimization work of the sizes, of the positions and of the doping of the portions constituting the parasitic diode Dp itself, in particular the wells 6a and 7a, respectively P-well and N-well, becomes mandatory so as to minimize the efficiency and in consequence its negative effects on the power actuator 1.
In reality, simulations carried out by the Applicant itself have proved that also a suitable design of the wells 6a and 7a is not enough to ensure a correct operation of the power actuator 1 due to the parasitic diode Dp.
In particular, by means of simulations of the flow lines of the current of electrons under direct bias conditions of the parasitic diode Dp, it has been verified that only a part of the electrons coming from the source region S of the DMOS transistor 3 succeed in being correctly used by the emitter region E, in particular the second buried layer 7, of the bipolar transistor 2 for sustaining the gain thereof, while a part of these electrons, which particularly move towards the first metallization layer 13, i.e., the contact of the base terminal B, through the parasitic diode Dp, withdraws a non-negligible amount of current from the bipolar transistor 2 thus creating a parasitic current and maintaining the worsening of the performances of the power actuator 1 at an unacceptable level.
In order to better understand the subdivision of the flow of electrons in correspondence with the P-well/N-well junction of the wells 6a and 7a which realize the parasitic diode Dp it is possible to refer to FIGS. 4A and 4B where an axonometrical view of an integrated structure of the power actuator 1, in particular in correspondence with its base terminal B and then with the parasitic diode Dp, is shown.
In particular, it is immediately verified that this flow of electrons occurs in correspondence with a contact area Zc (indicated by arrows in FIG. 4A) in correspondence with the junction between the first metallization layer 13 and the base contact well 6a, corresponding to a contact portion 13A, in particular a flat portion, of this first metallization layer 13 directly into contact, without oxide interposition, with the base contact well 6a. 
To better highlight this contact area Zc, in FIG. 4A the integrated structure of the power actuator 1 has been shown making both the first metallization layer 13 and the corresponding oxide portion 15 above the silicon transparent. In this way it is possible to easily recognize the P-well/N-well junction along a depth size Z of the integrated structure of the power actuator 1.
It is then shown how the distance of this P-well/N-well junction from the contact area Zc on the P-well 6a, in particular the extreme contact point Ec between the first metallization layer 13 and the oxide portion 15, is always constant, and equal in particular to Dl, as indicated in FIG. 4B, is mainly responsible for the migration of electrons towards the contact of the base terminal and then for the parasitic current of the parasitic diode Dp, which heavily limits the performances of the power actuator 1 thus realized.